Abstract

Jyoti Singh Chouhan, Nitin Jain

ABSTRACT

Floating point unit is an integral part of the next-generation processor. The fused Multiply-Add (FMA) the operation is used in many scientific and engineering applications. A key feature of floating point unit is, it greatly increases floating point performance and accuracy. Many floating-point fused multiply-add algorithm is used to reduce latency, the main objective of our work is to implement this algorithm with a little change to reduce the propagation of errors in an iterative process by using an additional error recovery circuit and to also increase the performance of block.